library verilog;
use verilog.vl_types.all;
entity uart_transmitter is
    generic(
        s_idle          : integer := 0;
        s_send_start    : integer := 1;
        s_send_byte     : integer := 2;
        s_send_parity   : integer := 3;
        s_send_stop     : integer := 4;
        s_pop_byte      : integer := 5
    );
    port(
        clk             : in     vl_logic;
        wb_rst_i        : in     vl_logic;
        lcr             : in     vl_logic_vector(7 downto 0);
        tf_push         : in     vl_logic;
        wb_dat_i        : in     vl_logic_vector(7 downto 0);
        enable          : in     vl_logic;
        stx_pad_o       : out    vl_logic;
        tstate          : out    vl_logic_vector(2 downto 0);
        tf_count        : out    vl_logic_vector(4 downto 0);
        tx_reset        : in     vl_logic;
        lsr_mask        : in     vl_logic
    );
end uart_transmitter;
